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Features:

HIGH-SPEED 2.5V ADVANCED 256/128K x 72 IDT70T3719/99M SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
- 1.7ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 166MHz - Data input, address, byte enable and control registers Separate byte controls for multiplexed bus and bus matching compatibility Dual Cycle Deselect (DCD) for Pipelined Output Mode 2.5V (100mV) power supply for core LVTTL compatible, selectable 3.3V (150mV) or 2.5V (100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40C to +85C) is available at 133MHz Available in a 324-pin Green Ball Grid Array (BGA) Includes JTAG Functionality

True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed data access - Commercial: 3.6ns (166MHz)/ 4.2ns (133MHz)(max.) - Industrial: 4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Interrupt and Collision Detection Flags Full synchronous operation on both ports - 6ns cycle time, 166MHz operation (23.9Gbps bandwidth) - Fast 3.6ns clock to data out - Self-timed write allows fast cycle time

Functional Block Diagram
BE7L BE7R
BE0L
BE0R
FT/PIPEL
1/0
0a 1a a
0h 1h h
1h 0h h
1a 0a a
1/0
FT/PIPER
R/WL
R/WR
CE0L CE1L
1 0 1/0 B W 0 L B W 7 L B W 7 R B W 0 R 1 0 1/0
CE0R CE1R
OEL
OER
DOUT0-8_L DOUT9-17_L DOUT18-26_L DOUT27-35_L DOUT36-44_L DOUT45-53_L DOUT54-62_L DOUT63-72_L 1h 0h 1a 0a a h
DOUT0-8_R DOUT9-17_R DOUT18-26_R DOUT27-35_R DOUT36-44_R DOUT45-53_R DOUT54-62_R DOUT63-72_R 0a 1a h a 0h 1h
0/1
,
FT/PIPER
FT/PIPEL
0/1
256/128K x 72 MEMORY ARRAY
Byte 0 I/O0L - I/O71L Byte 7 DIN_L DIN_R Byte 7 Byte 0 I/O0R - I/O71R
CLKL A17L (1) A0L REPEATL ADSL CNTENL A17R (1)
CLKR
,
Counter/ Address Reg.
ADDR_L
ADDR_R
Counter/ Address Reg.
A 0R REPEATR ADSR CNTENR
CE0L CE1L R/WL COL L INTL
(2)
INTERRUPT COLLISION DETECTION LOGIC
CE0R CE1R R/WR COL R INTR
TDI
JTAG
TDO
TCK TMS TRST
ZZL
ZZ CONTROL
ZZR
(2)
LOGIC NOTES: 1. Address A17 is a NC for the IDT70T3799. 2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
5687 drw 01
JUNE 2005
DSC 5687/1
1
(c)2005 Integrated Device Technology, Inc.
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Description:
The IDT70T3719/99M is a high-speed 256K/128K x 72 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70T3719/99M has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The 70T3719/99M can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device (VDD) is at 2.5V.
6.42 2
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Pin Configuration (2,3,4,5)
70T3719/99M BBG-324(6) 324-Pin BGA Top View(7)
06/27/05
1 I/O39R I/O39L I/O40R I/O40L I/O47R I/O47L I/O48R I/O48L I/O55R I/O55L I/O56R I/O56L I/O63R I/O63L I/O64R I/O64L I/O71R I/O71L 1
2 I/O38R I/O38L I/O41R I/O41L I/O46R I/O46L I/O49R I/O49L I/O54R I/O54L I/O57R I/O57L I/O62R I/O62L I/O65R I/O65L I/O70R I/O70L 2
3 I/O37R I/O37L I/O42R I/O42L I/O45R I/O45L I/O50R I/O50L I/O53R I/O53L I/O58R I/O58L I/O61R I/O61L I/O66R I/O66L I/O69R I/O69L 3
4 I/O36R I/O36L I/O43R I/O43L
5 COLL TDO INTL TDI
6 A15L A17L(1) A16L NC VDD VDD
7 A12L A13L A11L A14L VDDQL VDDQL Vs s Vs s Vs s Vs s Vs s Vs s VDDQL VDD A12R A13R A14R A15R 7
8 A8L A10L A7L A9L VDDQR Vs s Vs s Vs s Vs s Vs s Vs s Vs s VDDQL VDD A9R A7R A10R A11R 8
9 BE7L BE6L BE0L BE4L VDDQR Vs s Vs s Vs s Vs s Vs s Vs s Vs s Vs s VDD BE4R BE7R BE2R A8R 9
10 BE2L BE5L CE0L BE3L VDDQL Vs s Vs s Vs s Vs s Vs s Vs s Vs s Vs s VDDQL CE0R BE3R BE6R BE5R 10
11 CE1L BE1L
12 ADSL OEL
13 A6L
REPEATL
14 A1L A0L A3L ZZL OPTL VDD VDDQR VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR OPTR A1R A0R A3R A5R 14
15 I/O32R I/O32L I/O31R I/O31L I/O24R I/O24L I/O23R I/O23L I/O16R I/O16L I/O15R I/O15L I/O8R I/O8L I/O7R I/O7L I/O0R I/O0L 15
16 I/O33R I/O33L I/O30R I/O30L I/O25R I/O25L I/O22R I/O22L I/O17R I/O17L I/O14R I/O14L I/O9R I/O9L I/O6R I/O6L I/O1R I/O1L 16
17 I/O34R I/O34L I/O29R I/O29L I/O26R I/O26L I/O21R I/O21L I/O18R I/O18L I/O13R I/O13L I/O10R I/O10L I/O5R I/O5L I/O2R I/O2L 17
18 I/O35R I/O35L I/O28R I/O28L I/O27R I/O27L I/O20R I/O20L I/O19R I/O19L I/O12R I/O12L I/O11R I/O11L I/O4R I/O4L I/O3R I/O3L 18
5687 tbl 01
A B C D E F G H J K L M N P R T U V
A B C D E F G H J K L M N P R T U V
R/WL CNTENL CLKL VDDQL VDD Vs s Vs s Vs s Vs s Vs s Vs s VDD VDDQL OER CE1R BE1R BE0R 11 A5L VDDQR VDD Vs s Vs s Vs s Vs s Vs s Vs s VDDQR VDD A6R ADSR
A4L A2L VDDQR VDD VDDQR VDDQL Vs s Vs s Vs s VDDQL VDDQR VDD A2R A4R
I/O44R PL/FTL I/O44L I/O51R I/O51L I/O52R I/O52L I/O59R I/O59L I/O60R I/O60L I/O67R VDD
VDDQR VDDQR VDDQL VDDQR VDDQR VDDQL VDDQL VDDQL Vs s Vs s Vs s VDD
VDDQR VDDQR ZZR COLR TMS A17R(1)
I/O67L PL/FTR A16R I/O68R I/O68L 4 TCK TRST 5 INTR NC 6
R/WR REPEATR CLKR CNTENR 12 13
NOTES: 1. Pin is a NC for IDT70T3799. 2. All VDD pins must be connected to 2.5V power supply. 3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is set to VSS (0V). 4. All VSS pins must be connected to ground supply. 5. Package body is approximately 19mm x 19mm x 1.4mm, with 1.76mm ball-pitch. 6. This package code is used to reference the package diagram. 7. This text does not indicate orientation of the actual part-marking.
6.42 3
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0L, CE1L R/WL OEL A0L - A17L(5) I/O0L - I/O71L CLKL PL/FTL ADSL CNTENL REPEATL BE0L - BE7L VDDQL OPTL ZZL VDD VSS TDI TDO TCK TMS TRST INTL COLL INTR COLR Right Port CE0R, CE1R R/WR OER A0R - A17R(5) I/O0R - I/O71R CLKR PL/FTR ADSR CNTENR REPEATR BE0R - BE7R VDDQR OPTR ZZR Names Chip Enables (Input)(6) Read/Write Enable (Input) Output Enable (Input) Address (Input) Data Input/Output Clock (Input) Pipeline/Flow-Through (Input) Address Strobe Enable (Input) Counter Enable (Input) Counter Repeat(3) Byte Enables (9-bit bytes) (Input)(6) Power (I/O Bus) (3.3V or 2.5V)(1) (Input) Option for selecting VDDQX(1,2) (Input) Sleep Mode pin(4) (Input) Power (2.5V)(1) (Input) Ground (0V) (Input) Test Data Input Test Data Output Test Logic Clock (10MHz) (Input) Test Mode Select (Input) Reset (Initialize TAP Controller) (Input) Interrupt Flag (Output) Collision Alert (Output)
5687 tbl 02
NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another--both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. It is recommended that boundry scan not be operated during sleep mode. 5. Address A17x is a NC for the IDT70T3799M. 6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the signals take two cycles to deselect.
6.42 4
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Truth Table I--Read/Write and Enable Control
OE X X X X X X X L L L L H X X X CLK CE0 H X L L L L L L L L L X X CE1 X L H H H H H H H H H X X Byte Enables All BE = X All BE = X All BE = H BEn = L, All other BE = H BE4-7 = L, BE0-3 = H BE4-7 = H, BE0-3 = L BE0-7 = L BEn = L, All other BE = H BE4-7 = L, BE0-3 = H BE4-7 = H, BE0-3 = L All BE = L All BE = X All BE = X R/W X X X L L L L H H H H X X ZZ L L L L L L L L L L L L H
(1,2,3,4,5)
MODE Deselected: Power Down Deselected: Power Down All Bytes Deselected
I/O Operation(6) All Bytes= High-Z All Bytes = High-Z All Bytes = High-Z
Byten = DIN, All other Bytes = High-Z Write to Byte X Only Byte4-7 = DIN, Byte0-3 = High-Z Byte4-7 = High-Z, Byte0-3 = DIN Byte0-7 = DIN Write to Lower Bytes Only Write to Upper Bytes Only Write to All Bytes
Byten = DOUT, All other Bytes = High-Z Read Byte X Only Byte4-7 = DOUT, Byte0-3 = High-Z Byte4-7 = High-Z, Byte0-3 = DOUT All Bytes = DOUT All Bytes = High-Z All Bytes = High-Z Read Lower Bytes Only Read Upper Bytes Only Read All Bytes Outputs Disabled Sleep Mode
5687 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, REPEAT = Don't Care. See Truth Table II. 3. OE and ZZ are asynchronous input signals. 4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here. 5. For the examples shown here, BEn may correspond to any of the eight byte enable signals.
Truth Table II--Address Counter Control
Address An X X X Previous Internal Address X An An + 1 X Internal Address Used An An + 1 An + 1 An CLK ADS(4) L H H X CNTEN X L
(5)
(1,2)
REPEAT(4,6) H H H L
I/O(3) DI/O(n) External Address Used
MODE
DI/O(n+1) Counter Enabled-Internal Address generation DI/O(n+1) Enabled Address Blocked-Counter disabled (An + 1 reused) DI/O(n) Counter Set to last valid ADS load
5687 tbl 04
H X
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE. 3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn. 6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.42 5
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Recommended Operating Temperature and Supply Voltage
Grade Commercial Industrial Ambient Temperature 0 C to +70 C -40OC to +85OC
O O
(1)
GND 0V 0V
VDD 2.5V + 100mV 2.5V + 100mV
5687 tbl 05
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating Conditions with VDDQ at 2.5V
Symbol VDD VDDQ VSS VIH Parameter Core Supply Voltage I/O Supply Voltage (3) Ground Input High Volltage (Address, Control & Data I/O Inputs)(3) Input High Voltage JTAG
_
Min. 2.4 2.4 0 1.7
Typ. 2.5 2.5 0
____
Max. 2.6 2.6 0 VDDQ + 100mV (2)
Unit V V V V
VIH VIH VIL VIL
1.7 VDD - 0.2V -0.3(1) -0.3(1)
____
VDD + 100mV (2) VDD + 100mV (2) 0.7 0.2
V V V V
5687 tbl 06a
Input High Voltage ZZ, OPT, PIPE/FT Input Low Voltage Input Low Voltage ZZ, OPT, PIPE/FT
____
____
____
NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as indicated above.
Recommended DC Operating Conditions with VDDQ at 3.3V
Symbol VDD VDDQ VSS VIH Parameter Core Supply Voltage I/O Supply Voltage Ground Input High Voltage (Address, Control &Data I/O Inputs)(3) Input High Voltage JTAG
_ (3)
Min. 2.4 3.15 0 2.0
Typ. 2.5 3.3 0
____
Max. 2.6 3.45 0 VDDQ + 150mV (2)
Unit V V V V
VIH VIH VIL VIL
1.7 VDD - 0.2V -0.3
(1)
____
VDD + 100mV (2) VDD + 100mV (2) 0.8 0.2
V V V V
Input High Voltage ZZ, OPT, PIPE/FT Input Low Voltage Input Low Voltage ZZ, OPT, PIPE/FT
____
____
-0.3(1)
____
5687 tbl 06b
NOTES: 1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less. 2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less. 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied as indicated above.
6.42 6
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings (1)
Symbol VTERM (VDD) VTERM(2) (VDDQ) VTERM(2) (INPUTS and I/O's) TBIAS(3) TSTG TJN Rating VDD Terminal Voltage with Respect to GND VDDQ Terminal Voltage with Respect to GND Input and I/O Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Junction Temperature Commercial & Industrial -0.5 to 3.6 -0.3 to VDDQ + 0.3 -0.3 to VDDQ + 0.3 -55 to +125 -65 to +150 +150 50 40 Unit V V V
o o o
C C C
IOUT(For VDDQ = 3.3V) DC Output Current IOUT(For VDDQ = 2.5V) DC Output Current
mA mA
5687 tbl 07
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This is a steady-state DC parameter that applies after the power supply has reached its nominal operating value. Power sequencing is not necessary; however, the voltage on any Input or I/O pin cannot exceed VDDQ during power supply ramp up. 3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance (1)
Symbol CIN COUT
(2)
(TA = +25C, F = 1.0MHZ)
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 0V VOUT = 0V Max. 15 10.5 Unit pF pF
5687 tbl 08
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. COUT also references CI/O.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 2.5V 100mV)
70T3719/99M Symbol |ILI| |ILI| |ILO| VOL (3.3V) VOH (3.3V) VOL (2.5V) VOH (2.5V) Parameter Input Leakage Current(1) JTAG & ZZ Input Leakage Current Output Leakage Current Output Low Voltage
(1) (1) (1,3) (1,2)
Test Conditions VDDQ = Max., VIN = 0V to VDDQ VDD = Max., VIN = 0V to VDD CE0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ IOL = +4mA, VDDQ = Min. IOH = -4mA, VDDQ = Min. IOL = +2mA, VDDQ = Min. IOH = -2mA, VDDQ = Min.
Min.
___
Max. 10 30 10 0.4
___
Unit A A A V V V V
5687 tbl 09
___
___
___
Output High Voltage
2.4
___
Output Low Voltage (1) Output High Voltage (1)
0.4
___
2.0
NOTES: 1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details. 2. Applicable only for TMS, TDI and TRST inputs. 3. Outputs tested in tri-state mode.
6.42 7
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (3) (VDD = 2.5V 100mV)
70T3719/99M S166 Com'l Only Symbol IDD Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) Standby Current (One Port - TTL Level Inputs) Full Standby Current (Both Ports - CMOS Level Inputs) Full Standby Current (One Port - CMOS Level Inputs) Sleep Mode Current (Both Ports - TTL Level Inputs) CEL and CER= VIL, Outputs Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX(1) CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(1) Both Ports CEL and CER > VDDQ - 0.2V, VIN > VDDQ - 0.2V or VIN < 0.2V, f = 0(2) CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5) VIN > VDDQ - 0.2V or VIN < 0.2V Active Port, Outputs Disabled, f = fMAX(1) ZZL = ZZR = VIH f=fMAX(1) Test Condition Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S S S S S S S S S S S S Typ. (4) 640
___
70T3719/99M S133 Com'l & Ind Typ. (4) 520 520 280 280 400 400 12 12 400 400 12 12 Max. 740 mA 900 380 mA 470 500 mA 620 20 mA 25 500 mA 620 20 mA 25
5687 tbl 10
Max. 900
___
Unit
ISB1(6)
350
___
460
___
ISB2(6)
500
___
650
___
ISB3
12
___
20
___
ISB4(6)
500
___
650
___
Izz
12
___
20
___
NOTES: 1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS". 2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4. VDD = 2.5V, TA = 25C for Typ, and are not production tested. IDD DC(f=0) = 30mA (Typ). 5. CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X - 0.2V "X" represents "L" for left port or "R" for right port. 6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
6.42 8
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V/GND to 2.4V GND to 3.0V/GND to 2.4V 2ns 1.5V/1.25V 1.5V/1.25V Figure 1
5687 tbl 11
50 DATAOUT
50 1.5V/1.25 10pF (Tester)
,
5687 drw 03
Figure 1. AC Output Test load.
tCD
(Typical, ns)
Capacitance (pF) from AC Test Load
5687 drw 04
6.42 9
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range (Read and Write Cycle Timing) (2,3) (VDD = 2.5V 100mV, TA = 0C to +70C)
70T3719/99M S166 Com'l Only Symbol tCYC1 tCYC2 tCH1 tCL1 tCH2 tCL2 tSA tHA tSC tHC tSB tHB tSW tHW tSD tHD tSAD tHAD tSCN tHCN tSRPT tHRPT tOE tOLZ(4) tOHZ tCD1 tCD2 tDC tCKHZ
(4) (4)
70T3719/99M S133 Com'l & Ind Min. 25 7.5 10 10 3 3 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5 1.8 0.5
____
Parameter Clock Cycle Time (Flow-Through)(1) Clock Cycle Time (Pipelined)
(1)
Min. 20 6 8 8 2.4 2.4 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5 1.7 0.5
____
Max.
____ ____
Max.
____ ____
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cycles cycles
Clock High Time (Flow-Through)(1) Clock Low Time (Flow-Through)(1) Clock High Time (Pipelined)(2) Clock Low Time (Pipelined) Address Setup Time Address Hold Time Chip Enable Setup Time Chip Enable Hold Time Byte Enable Setup Time Byte Enable Hold Time R/W Setup Time R/W Hold Time Input Data Setup Time Input Data Hold Time ADS Setup Time ADS Hold Time CNTEN Setup Time CNTEN Hold Time REPEAT Setup Time REPEAT Hold Time Output Enable to Data Valid Output Enable to Output Low-Z Output Enable to Output High-Z Clock to Data Valid (Flow-Through)(1) Clock to Data Valid (Pipelined)(1) Data Output Hold After Clock High Clock High to Output High-Z Clock High to Output Low-Z Interrupt Flag Set Time Interrupt Flag Reset Time Collision Flag Set Time Collision Flag Reset Time Sleep Mode Set Cycles Sleep Mode Recovery Cycles
(1)
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____ ____ ____
____
____
____
____
____
____
____
____
____
____
____
____
4.4
____
4.6
____
1 1
____ ____
1 1
____ ____
3.6 12 3.6
____
4.2 15 4.2
____
1 1 1
____ ____
1 1 1
____ ____
3.6
____
4.2
____
tCKLZ(4) tINS tINR tCOLS tCOLR tZZSC tZZRC
7 7 3.6 3.6
____ ____
7 7 4.2 4.2
____ ____
____ ____
____ ____
2 3
2 3
Port-to-Port Delay tCO tOFS Clock-to-Clock Offset Clock-to-Clock Offset for Collision Detection 5
____
6
____
ns
Please refer to collision Detection Timing Table on Page 19.
5687 tbl 12
NOTES: 1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1) apply when FT/PIPE = Vss (0V) for that port. 2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be treated as DC signals, i.e. steady state during operation. 3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port. 4. Guaranteed by design (not production tested).
6.42 10
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation (FT/PIPE'X' = VIH)(1,2)
tCYC2 tCH2 CLK
CE0
tCL2
tSC CE1 tSB
BEn
tHC
tSC
(3)
tHC
tHB
tSB
(5)
tHB
R/W
tSW tHW tSA tHA An + 1 (1 Latency) tCD2 Qn tCKLZ
(1)
ADDRESS
(4)
An
An + 2 tDC Qn + 1
An + 3
DATAOUT
Qn + 2 tOLZ
(5)
tOHZ
OE
(1)
tOE
5687 drw 05
,
Timing Waveform of Read Cycle for Flow-through Output (FT/PIPE"X" = VIL)(1,2,6)
tCYC1 tCH1 CLK
CE0
tCL1
tSC CE1 tSB
BEn
tHC
tSC
(3)
tHC
tHB tSB tHB
R/W
tSW tHW tSA tHA An + 1 tCD1 tDC Qn tCKLZ Qn + 1 tOHZ tOLZ Qn + 2 An + 2 An + 3 tCKHZ
(5)
ADDRESS
(4)
An
DATAOUT
tDC
OE
(1)
5687 drw 06 NOTES: 1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge. 2. ADS = VIL, CNTEN and REPEAT = VIH. 3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to Truth Table 1. 4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state). 6. "x" denotes Left or Right port. The diagram is with respect to that port.
tOE
,
6.42 11
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read
tCYC2 tCH2 CLK tSA ADDRESS(B1) tSC
CE0(B1)
(1,2)
tCL2
tHA A0 tHC tSC tCD2 tHC tCD2 Q0 tDC Q1 tDC A4 tCKLZ A5 tCKHZ tCD2 Q3 tCKHZ A6 A1 A2 A3 A4 A5 A6
DATAOUT(B1) tSA ADDRESS(B2) tHA A0 A1
A2
A3
tSC
CE0(B2)
tHC
tSC
tHC tCD2 tCKHZ Q2 tCKLZ tCKLZ
5687 drw 07
tCD2
,
DATAOUT(B2)
Q4
Timing Waveform of a Multi-Device Flow-Through Read
tCH1 CLK tSA ADDRESS(B1) tH
A
(1,2)
tCYC1 tCL1
A0 tSC tHC
A1
A2
A3
A4
A5
A6
CE0(B1)
tSC tHC tCD1 tCD1 D0 tDC tSA tHA A0 A1 A2 A3 A4 A5 A6 tCKHZ D1 tDC
(1)
tCD1 D3 tCKLZ
(1)
tCD1 D5 tCKHZ(1) tCKLZ
(1)
DATAOUT(B1)
ADDRESS(B2)
tSC tHC CE0(B2) tSC tHC tCD1 DATAOUT(B2) tCKLZ
(1)
tCKHZ D2
(1)
tCD1 tCKLZ
(1)
tCKHZ D4
(1)
, 5687 drw 08
NOTES: 1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3719/99M for this waveform, and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation. 2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42 12
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read
CLK"A" tSW R/W"A
"
(1,2,4)
tHW
tSA ADDRESS"A"
tHA
NO MATCH
MATCH
tSD DATAIN"A"
tHD
VALID
tCO(3) CLK"B" tCD2 R/W"B" tSW tSA ADDRESS"B" tHW tHA
NO MATCH
MATCH
DATAOUT"B"
VALID
5687 drw 09 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port will be tCO + tCYC2 + tCD2). 4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
tDC
,
Timing Waveform with Port-to-Port Flow-Through Read
CLK "A" tSW tHW R/W "A" tSA ADDRESS "A" tHA
NO MATCH
(1,2,4)
MATCH
tSD DATAIN
"A"
tHD
VALID
tCO CLK "B"
(3)
tCD1 R/W "B" tSW tSA ADDRESS "B" tHW tHA
NO MATCH
MATCH
tCD1 DATAOUT "B" tDC
VALID VALID
tDC
,
5687 drw 10 NOTES: 1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to. 3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will be tCO + tCD1). 4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.42 13
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read tCYC2 (OE = VIL)(2)
tCH2 tCL2 CLK
CE0
tSC tHC CE1 tSB
BEn
tHB
tSW tHW R/W tSW tHW
ADDRESS
(3)
An tSA tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
DATAIN
(1)
tCD2 Qn
tCKHZ
tCKLZ
tCD2 Qn + 3
DATAOUT READ
NOP
(4)
WRITE
READ
5687 drw 11 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation". 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)
tCH2 CLK
CE0
(2)
tCYC2 tCL2
tSC tHC CE1 tSB
BEn
tHB
tSW tHW R/W tSW tHW
ADDRESS
(3)
An tSA tHA
An +1
An + 2 tSD tHD
An + 3
An + 4
An + 5
DATAIN
(1)
tCD2 Qn tOHZ
(4)
Dn + 2
Dn + 3
tCKLZ
tCD2 Qn + 4
DATAOUT
OE
, NOTES: 5687 drw 12 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
READ
WRITE
READ
6.42 14
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
tCH1 CLK tCYC1 tCL1
CE0
tSC tHC CE1 tSB
BEn
tHB
tSW tHW R/W tSW tHW
ADDRESS
(3)
tSA DATAIN
(1)
An tHA
An +1
An + 2
An + 2 tSD tHD Dn + 2
An + 3
An + 4
tCD1 Qn tDC READ
tCD1 Qn + 1 tCKHZ NOP
(5)
tCD1
tCD1 Qn + 3 tDC READ
DATAOUT
tCKLZ WRITE
, 5687 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
tCYC1 tCH1 tCL1 CLK
CE0
tSC tHC CE1 tSB
BEn
tHB
tSW tHW R/W ADDRESS
(3)
tSW tHW An tSA tHA An +1 An + 2 tSD tHD Dn + 2
(1)
An + 3
An + 4
An + 5
DATAIN tCD1 Qn tOHZ
OE
Dn + 3
tDC
tOE tCD1 tCKLZ
tCD1 Qn + 4 tDC
DATAOUT
READ WRITE READ 5687 drw 14 NOTES: 1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals. 2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. 3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use only. 4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
,
6.42 15
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
(1)
An tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN tCD2
DATAOUT
Qx - 1(2)
Qx tDC
Qn
Qn + 1
Qn + 2(2)
,
Qn + 3
READ EXTERNAL ADDRESS
READ WITH COUNTER
COUNTER HOLD
READ WITH COUNTER
5687 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance
tCYC1 tCH1 tCL1 CLK tSA ADDRESS tHA
(1)
An tSAD tHAD
ADS
tSAD tHAD tSCN tHCN
CNTEN
tCD1 DATAOUT Qx(2) tDC READ EXTERNAL ADDRESS READ WITH COUNTER COUNTER HOLD READ WITH COUNTER
5687 drw 16
Qn
Qn + 1
Qn + 2
Qn + 3(2)
,
Qn + 4
NOTES: 1. CE0, OE, BEn = VIL; CE1, R/W, and REPEAT = VIH. 2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains constant for subsequent clocks.
6.42 16
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance (Flow-through or Pipelined Inputs) (1)
tCH2 CLK tSA ADDRESS tHA tCYC2 tCL2
An
INTERNAL(3) ADDRESS tSAD tHAD
ADS
An(7)
An + 1
An + 2
An + 3
An + 4
tSCN tHC
CNTEN
N
tSD tHD DATAIN Dn WRITE EXTERNAL ADDRESS Dn + 1 Dn + 1 Dn + 2 Dn + 3 Dn + 4
WRITE WRITE WITH COUNTER COUNTER HOLD
WRITE WITH COUNTER
5687 drw 17
,
Timing Waveform of Counter Repeat
tCYC2 CLK tSA tHA ADDRESS INTERNAL ADDRESS
ADS
(3)
(2,6)
An An tSAD tHAD tSW tHW An+1 An+2 An+2 An An+1 An+2 An+2
R/W tSCN tHCN
CNTEN
(4)
REPEAT
tSRPT tHRPT
,
tSD tHD DATAIN D0 D1 D2 D3 tCD1 DATAOUT WRITE TO ADS ADDRESS An ADVANCE COUNTER WRITE TO An+1 ADVANCE COUNTER WRITE TO An+2 HOLD COUNTER WRITE TO An+2 An REPEAT READ LAST ADS ADDRESS An An+1 ADVANCE COUNTER READ An+1 An+2
,
An+2 HOLD COUNTER READ An+2
5687 drw 18
ADVANCE COUNTER READ An+2
NOTES: 1. CE0, BEn, and R/W = VIL; CE1 and REPEAT = VIH. 2. CE0, BEn = VIL; CE1 = VIH. 3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH. 4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid ADS load will be accessed. For more information on REPEAT function refer to Truth Table II. 5. CNTEN = VIL advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is written to during this cycle. 6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
6.42 17
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing
CLKL tSW R/WL tSA ADDRESSL(3) tHA tHW
(2)
3FFFF
tSC CEL
(1)
tHC
tINS INTR tINR tSC CER(1) tHC
CLKR
R/WR tSW tSA ADDRESSR(3) tHW tHA
3FFFF
5687 drw 19
NOTES: 1. CE0 = VIL and CE1 = VIH 2. All timing is the same for Left and Right ports. 3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Truth Table III -- Interrupt Flag
Left Port CLKL R/WL L X X H CEL L X X L A17L-A0L
(3,4)
(1)
Right Port
INTL X X L H
CLKR
R/WR X X L X
(2)
CER X L L X
(2)
A17R-A0R(3,4) X 3FFFF 3FFFE X
INTR L H X X
Function Set Right INTR Flag Reset Right INTR Flag Set Left INTL Flag Reset Left INTL Flag
5687 tbl 13
3FFFF X X 3FFFE
NOTES: 1. INTL and INTR must be initialized at power-up by Resetting the flags. 2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 3. A17X is a NC for IDT70T3799, therefore Interrupt Addresses are 1FFFF and 1FFFE. 4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42 18
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Waveform of Collision Timing(1,2) Both Ports Writing with Left Port Clock Leading
CLKL tOFS tSA ADDRESSL
(4)
tHA A0 A1 A2 A3
tCOLS COLL
(3)
tCOLR
tOFS CLKR
tSA ADDRESSR
(4)
tHA A0 A1 A2 A3
tCOLS COLR
tCOLR
5687 drw 20
NOTES: 1. CE0 = VIL, CE1 = VIH. 2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases. 3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match. 4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
Cycle Time Region 1 (ns) 5ns 6ns 7.5ns 0 - 2.8 0 - 3.8 0 - 5.3
(1)
tOFS (ns)
Region 2 (ns) 2.81 - 4.6 3.81 - 5.6 5.31 - 7.1
56876 tbl 14
(2)
NOTES: 1. Region 1 Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc. 2. Region 2 Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc. while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc. 3. All the production units are tested to midpoint of each region. 4. These ranges are based on characterization of a typical device.
Truth Table IV -- Collision Detection Flag
Left Port CLKL R/WL H H L L CEL L L L L A17L-A0L
(2)
Right Port COLL H L H L CLKR R/WR H L H L
(1)
CER(1) L L L L
A17R-A0R(2) MATCH MATCH MATCH MATCH
COLR H H L L
Function Both ports reading. Not a valid collision. No flag output on either port Left port reading, Right port writing. Valid collision, flag output on Left port. Right port reading, Left port writing. Valid collision, flag output on Right port. Both ports writing. Valid collision. Flag output on both ports.
5687 tbl 15
MATCH MATCH MATCH MATCH
NOTES: 1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times. 2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42 19
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Timing Waveform - Entering Sleep Mode (1,2)
R/W
(3)
Timing Waveform - Exiting Sleep Mode
(1,2)
An
An+1
(5)
R/W
OE
(5)
DATAOUT
Dn
Dn+1
(4)
NOTES: 1. CE1 = VIH. 2. All timing is same for Left and Right ports. 3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH). 4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL). 5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42 20
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Functional Description
The IDT70T3719/99M provides a true synchronous Dual-Port Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse width is independent of the cycle time. An asynchronous output enable is provided to ease asynchronous bus interfacing. Counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. A HIGH on CE0 or a LOW on CE1 for one clock cycle will power down the internal circuitry to reduce static power consumption. Multiple chip enables allow easier banking of multiple IDT70T3719/99Ms for depth expansion configurations. Two cycles are required with CE0 LOW and CE1 HIGH to re-activate the outputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. The left port interrupt flag (INTL) is asserted when the right port writes to memory location 3FFFE (HEX), where a write is defined as CER = R/WR = VIL per the Truth Table I. The left port clears the interrupt through access of address location 3FFFE when CEL = VIL and R/WL = VIH. Likewise, the right port interrupt flag (INTR) is asserted when the left port writes to memory location 3FFFF (HEX) and to clear the interrupt flag (INTR), the right port must read the memory location 3FFFF (1FFFF or 1FFFE for IDT70T3799M). The message (72 bits) at 3FFFE or 3FFFF (1FFFF or 1FFFE for 70T3799M) is user-defined since it is an addressable SRAM location. If the interrupt function is not used, address locations 3FFFE and 3FFFF (1FFFF or 1FFFE for IDT70T3799M) are not used as mail boxes, but as part of the random access memory. Refer to Truth Table III for the interrupt operation.
alert flag as appropriate. In the event that a user initiates a burst access on both ports with the same starting address on both ports and one or both ports writing during each access (i.e., imposes a long string of collisions on contiguous clock cycles), the alert flag will be asserted and cleared every other cycle. Please refer to the Collision Detection timing waveform on Page 19. Collision detection on the IDT70T3719/99M represents a significant advance in functionality over current sync multi-ports, which have no such capability. In addition to this functionality the IDT70T3719/99M sustains the key features of bandwidth and flexibility. The collision detection function is very useful in the case of bursting data, or a string of accesses made to sequential addresses, in that it indicates a problem within the burst, giving the user the option of either repeating the burst or continuing to watch the alert flag to see whether the number of collisions increases above an acceptable threshold value. Offering this function on chip also allows users to reduce their need for arbitration circuits, typically done in CPLD's or FPGA's. This reduces board space and design complexity, and gives the user more flexibility in developing a solution.
Sleep Mode
The IDT70T3719/99M is equipped with an optional sleep or low power mode on both ports. The sleep mode pin on both ports is asynchronous and active high. During normal operation, the ZZ pin is pulled low. When ZZ is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. The sleep mode timing diagram shows the modes of operation: Normal Operation, No Read/Write Allowed and Sleep Mode. For normal operation all inputs must meet setup and hold times prior to sleep and after recovering from sleep. Clocks must also meet cycle high and low times during these periods. Three cycles prior to asserting ZZ (ZZx = VIH) and three cycles after de-asserting ZZ (ZZx = VIL), the device must be disabled via the chip enable pins. If a write or read operation occurs during these periods, the memory array may be corrupted. Validity of data out from the RAM cannot be guaranteed immediately after ZZ is asserted (prior to being in sleep). When exiting sleep mode, the device must be in Read mode (R/Wx = VIH)when chip enable is asserted, and the chip enable must be valid for one full cycle before a read will result in the output of valid data. During sleep mode the RAM automatically deselects itself. The RAM disconnects its internal clock buffer. The external clock may continue to run without impacting the RAMs sleep current (IZZ). All outputs will remain in high-Z state while in sleep mode. All inputs are allowed to toggle. The RAM will not be selected and will not perform any reads or writes.
Collision Detection
Collision is defined as an overlap in access between the two ports resulting in the potential for either reading or writing incorrect data to a specific address. For the specific cases: (a) Both ports reading - no data is corrupted, lost, or incorrectly output, so no collision flag is output on either port. (b) One port writing, the other port reading - the end result of the write will still be valid. However, the reading port might capture data that is in a state of transition and hence the reading port's collision flag is output. (c) Both ports writing - there is a risk that the two ports will interfere with each other, and the data stored in memory will not be a valid write from either port (it may essentially be a random combination of the two). Therefore, the collision flag is output on both ports. Please refer to Truth Table IV for all of the above cases. The alert flag (COLX) is asserted on the 2nd or 3rd rising clock edge of the affected port following the collision, and remains low for one cycle. Please refer to Collision Detection Timing table on Page 19. During that next cycle, the internal arbitration is engaged in resetting the alert flag (this avoids a specific requirement on the part of the user to reset the alert flag). If two collisions occur on subsequent clock cycles, the second collision may not generate the appropriate alert flag. A third collision will generate the
6.42 21
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70T3719/99M features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth.
The IDT70T3719/99M can also be used in applications requiring expanded width, as indicated in Figure 4. Through combining the control signals, the devices can be grouped as necessary to accommodate applications needing 144-bits.
A18/A17(1)
IDT70T3719/99M
CE0 CE1 VDD
IDT70T3719/99M
CE0 CE1 VDD
Control Inputs
Control Inputs
IDT70T3719/99M
CE1 CE0
IDT70T3719/99M
CE1 CE0 BE, R/W, OE, CLK, ADS, REPEAT, CNTEN
Control Inputs
Control Inputs
Figure 4. Depth and Width Expansion with IDT70T3719/99M
5687 drw 23
,
NOTE: 1. A18 is for IDT70T3719, A17 is for IDT70T3799.
JTAG Functionality and Configuration
The IDT70T3719/99M is composed of two independent memory arrays, and thus cannot be treated as a single JTAG device in the scan . chain. The two arrays (A and B) each have identical characteristics and commands but must be treated as separate entities in JTAG operations. Please refer to Figure 5. JTAG signaling must be provided serially to each array and utilize the information provided in the Identification Register Definitions, Scan Register Sizes, and System Interface Parameter tables. Specifically, commands for Array B must precede those for Array A in any JTAG operations sent to the IDT70T3719/99M. Please reference Application Note AN-411, "JTAG Testing of Multichip Modules" for specific instructions on performing JTAG testing on the IDT70T3719/99M. AN-411 is available at www.idt.com.
IDT70T3719/99M
TDI TDOA TDIB TDO
Array A
Array B
TCK TMS TRST
5687 drw 24
Figure 5. JTAG Configuration for IDT70T3719/99M
6.42 22
IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJF TCK tJCL tJCYC tJR tJCH
Device Inputs(1)/ TDI/TMS tJS Device Outputs(2)/ TDO TRST
5687 drw 25
tJH
tJDC
tJRSR
tJCD ,
tJRST
Figure 5. Standard JTAG Timing
NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = All device outputs except TDO.
JTAG AC Electrical Characteristics (1,2,3,4)
70T3719/99M Symbol tJCYC tJCH tJCL tJR tJF tJRST tJRSR tJCD tJDC tJS tJH Parameter JTAG Clock Input Period JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery JTAG Data Output JTAG Data Output Hold JTAG Setup JTAG Hold Min. 100 40 40
____
Max.
____
Units ns ns ns ns ns ns ns ns ns ns ns
5687 tbl 16
____
____
3 3
(1) (1)
____
50 50
____
____
____
25
____
0 15 15
____
____
NOTES: 1. Guaranteed by design. 2. 30pF loading on external output signals. 3. Refer to AC Electrical Test Conditions stated earlier in this document. 4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
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IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field Array B
Revision Number (31:28) IDT Device ID (27:12)(1) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0)
Value
Array B 0x0 0x330 0x33 1
Instruction Field Array A
Revision Number (63:60) IDT Device ID (59:44)(1) IDT JEDEC ID (43:33) ID Register Indicator Bit (Bit 32)
Value
Array A 0x0 0x330 0x33 1
Description
Reserved for Version number Defines IDT Part number Allows unique identification of device vendor as IDT Indicates the presence of an ID Register
5687 tbl 17
NOTE: 1. Device ID for IDT70T3719M is 0x330. Device ID for IDT70T3799M is 0x331.
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size Array A 4 1 32 Note (3) Bit Size Array B 4 1 32 Note (3) Bit Size 70T3719M 8 2 64 Note (3)
5687 tbl 18
System Interface Parameters
Instruction EXTEST BYPASS IDCODE Code 00000000 11111111 00100010 01000100 Description Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers except INTx and COLx to a High-Z state. Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above.
HIGHZ CLAMP SAMPLE/PRELOAD
00110011 00010001
RESERVED
01010101, 01110111, 10001000, 10011001, 10101010, 10111011, 11001100 01100110,11101110, 11011101
PRIVATE
For internal use only.
5687 tbl 19
NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST. 3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative.
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IDT70T3719/99M High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM
Advanced Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A A Process/ Temperature Range
Blank I
Commercial (0C to +70C) Industrial (-40C to +85C)
G
Green
BB
324-pin BGA (BBG-324)
166 133
Commercial Only Commercial & Industrial
Speed in Megahertz
S
Standard Power
70T3719M 70T3799M
18Mbit (256K x 72) 2.5V Synchronous Dual-Port RAM 9Mbit (128K x 72) 2.5V Synchronous Dual-Port RAM
5687 drw 26
IDT Clock Solution for IDT70T3719/99M Dual-Port
Dual-Port I/O Specitications IDT Dual-Port Part Number Voltage I/O Input Capacitance Clock Specifications Input Duty Cycle Requirement 40% Maximum Frequency Jitter Tolerance IDT PLL Clock Device IDT Non-PLL Clock Device 5T9010 5T905, 5T9050 5T907, 5T9070
5687 tbl 20
70T3719/99M
3.3/2.5
LVTTL
15pF
166
75ps
5T2010
Datasheet Document History:
06/27/05: Initial Advanced Datasheet
CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138
for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
for Tech Support: 408-284-2794 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
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